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FBL22031 9-bit BTL 3.3V latched/registered/pass-thru Futurebus+ transceiver with 30 termination
Product specification Supersedes data of 1998 Sep 04 2000 Apr 18
Philips Semiconductors
Philips Semiconductors
Product specification
9-bit BTL 3.3V latched/registered/pass-thru Futurebus+ transceiver with 30 termination
FBL22031
FEATURES
path
* Latched, registered or straight through in either A to B or B to A * Drives heavily loaded backplanes with equivalent load
impedances down to 10.
* High drive 100mA BTL open collector drivers on B-port * Allows incident wave switching in heavily loaded backplane buses * Reduced BTL voltage swing produces less noise and reduces
power consumption
* Tight output skew * Supports live insertion * Pins for the optional JTAG boundary scan function are provided * High density packaging in plastic Quad Flatpack * 5V compatible I/O on A-port * Same pinout and function as the FBL2033 except for 30 series
termination
* The A output includes a a series resistor of 30 making external
terminating resistors unnecessary
* Built-in precision band-gap reference provides accurate receiver
thresholds and improved noise immunity
* Compatible with IEEE Futurebus+ or proprietary BTL backplanes * Each BTL driver has a dedicated Bus GND for a signal return * Controlled output ramp and multiple GND pins minimize ground
bounce
DESCRIPTION
The FBL22031 is a 9-bit latched/registered transceiver featuring a latched, registered or pass-thru mode in either the A-to-B or B-to-A direction. The FBL22031 is designed with a 30 series resistor in both the HIGH and LOW states of the output. The FBL22031 is intended to provide the electrical interface to a high performance wired-OR bus.
* Glitch-free power up/power down operation * Low ICC current
QUICK REFERENCE DATA
SYMBOL tPLH tPHL tPLH tPHL CO IOL ICC Propagation delay An to Bn Propagation delay Bn to An Output capacitance (B0 - Bn only) Output current (B0 - Bn only) PARAMETER
TYPICAL 2.7 4.4 4.2 6 100
UNIT ns ns pF mA mA
AIn to Bn (outputs Low or High) Supply current Bn to AOn (outputs Low) Bn to AOn (outputs High)
11 22 18
ORDERING INFORMATION
PACKAGE 52-pin Plastic Quad Flat Pack (PQFP) VCC = 3.3V10%; Tamb = -40C to +85C FBL22031BB DWG No. SOT379-1
2000 Apr 18
2
853-2119 23499
Philips Semiconductors
Product specification
9-bit BTL 3.3V latched/registered/pass-thru Futurebus+ transceiver with 30 termination
FBL22031
PIN CONFIGURATION
TMS (option) TCK (option) LOGIC GND BIAS V BUS GND
OEB0
OEA
OEB1
VCC
A1
A0
VCC
52 51 50 49 48 47 46 45 44 43 42 41 40 LOGIC GND A2 LOGIC GND A3 LOGIC GND A4 LOGIC GND A5 LOGIC GND A6 LOGIC GND A7 LOGIC GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 A8 SEL1 16 17 18 19 20 21 22 23 24 25 26 TDI (option) TDO (option) BUS GND BG GND SEL0 BG VCC LCBA LCAB VCC B8 B7 39 38 37 36 BUS GND B1 BUS GND B2 BUS GND B3 BUS GND B4 BUS GND B5 BUS GND B6 BUS GND
9-Bit latched/registered transceiver FBL22031
B0 35 34 33 32 31 30 29 28 27
52-lead PQFP
SG00091
PIN DESCRIPTION
SYMBOL A0 - A8 B0 - B8 OEB0 OEB1 OEA BUS GND LOGIC GND VCC BIAS V BG VCC BG GND SEL0 SEL1 LCAB LCBA TMS TCK TDI TDO PIN NUMBER 50, 52, 2, 4, 6, 8, 10, 12, 14 40, 38, 36, 34, 32, 30, 28, 26, 24 46 45 47 25, 27, 29, 31, 33, 35, 37, 39, 41 51, 1, 3, 5, 7, 9, 11, 13 23, 43, 49 48 17 19 20 15 18 16 42 44 22 21 TYPE I/O I/O Input Input Input GND GND Power Power Power GND Input Input Input Input Input Input Input Output NAME AND FUNCTION BiCMOS data inputs/3-State outputs (TTL) Data inputs/Open Collector outputs, High current drive (BTL) Enables the B outputs when High Enables the B outputs when Low Enables the A outputs when High Bus ground (0V) Logic ground (0V) Positive supply voltage Live insertion pre-bias pin Band Gap threshold voltage reference Band Gap threshold voltage reference ground Mode select Mode select A to B clock/latch enable (transparent latch when Low) B to A clock/latch enable (transparent latch when Low) Test Mode Select (optional, if not implemented then no connect) Test Clock (optional, if not implemented then no connect) Test Data In (optional, if not implemented then no connect) Test Data Out (optional, if not implemented then shorted to TDI)
2000 Apr 18
3
Philips Semiconductors
Product specification
9-bit BTL 3.3V latched/registered/pass-thru Futurebus+ transceiver with 30 termination
FBL22031
DESCRIPTION
The TTL-level side (A port) has a common I/O. The common I/O, open collector B port operates at BTL signal levels. The logic element for data flow in each direction is controlled by two mode select inputs (SEL0 and SEL1). A "00" configures latches in both directions. A "10" configures thru mode in both directions. A "01" configures register mode in both directions. A "11" configures register mode in the A-to-B direction and latch mode in the B-to-A direction. When configured in the buffer mode, the inverse of the input data appears at the output port. In the register mode, data is stored on the rising edge of the appropriate clock input (LCAB or LCBA). In the latch mode, clock pins serve as transparent-Low latch enables. Regardless of the mode, data is inverted from input to output. The 3-State A port is enabled by asserting a High level on OEA. The B port has two output enables, OEB0 and OEB1. Only when OEB0 is High and OEB1 is Low is the output enabled. When either OEB0 is Low or OEB1 is High, the B port is inactive and is pulled to the level of the pull-up voltage. New data can be entered in the register and latched modes or can be retained while the associated outputs are in 3-State (A port) or inactive (B port). The B-port drivers are Low-capacitance open collectors with controlled ramp and are designed to sink 100mA. Precision band gap references on the B-port insure very good noise margins by limiting the switching threshold to a narrow region centered at 1.55V. The B-port interfaces to "Backplane Transceiver Logic" (see the IEEE 1194.1 BTL standard). BTL features low power consumption by reducing voltage swing (1V p-p, between 1V and 2V) and reduced capacitive loading by placing an internal series diode on the
drivers. BTL also provides incident wave switching, a necessity for high performance backplanes. Output clamps are provided on the BTL outputs to further reduce switching noise. The "VOH" clamp reduces inductive ringing effects during a Low-to-High transition. The "VOH" clamp is always active. The other clamp, the "trapped reflection" clamp, clamps out ringing below the BTL 0.5V VOL level. This clamp remains active for approximately 100ns after a High-to-Low transition. To support live insertion, OEB0 is held Low during power on/off cycles to insure glitch- free B port drivers. Proper bias for B port drivers during live insertion is provided by the BIAS V pin when at a 3.3V level while VCC is Low. The BIAS V pin is a low current input which will reverse-bias the BTL driver series Schottky diode, and also bias the B port output pins to a voltage between 1.62V and 2.1V. This bias function is in accordance with IEEE BTL Standard 1194.1. If live insertion is not a requirement, the BIAS V pin should be tied to a VCC pin. The LOGIC GND and BUS GND pins are isolated inside the package to minimize noise coupling between the BTL and TTL sides. These pins should be tied to a common ground external to the package. Each BTL driver has an associated BUS GND pin that acts as a signal return path and these BUS GND pins are internally isolated from each other. In the event of a ground return fault, a "hard" signal failure occurs instead of a pattern dependent error that may be infrequent and impossible to troubleshoot. As with any high power device, thermal considerations are critical. It is recommended that airflow (300Ifpm) and/or thermal mounting be used to ensure proper junction temperature.
PACKAGE THERMAL CHARACTERISTICS
PARAMETER ja ja jc Still air 300 Linear feet per minute air flow Thermally mounted on one side to heat sink CONDITION 52-PIN PLASTIC QFP 80C/W 58C/W 20C/W
2000 Apr 18
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Philips Semiconductors
Product specification
9-bit BTL 3.3V latched/registered/pass-thru Futurebus+ transceiver with 30 termination
FBL22031
FUNCTION TABLE
MODE An to Bn thru mode An to Bn transparent latch An to Bn latch and read Bn outputs latched and read (preconditioned latch) An to Bn register Bn to An thru mode INPUTS An L H L H l h X l h -- -- -- Bn to An transparent latch -- -- -- -- Bn to An latch and read -- -- -- An outputs latched and read (preconditioned latch) -- -- -- -- X X X Bn* -- -- -- -- -- -- -- -- -- L H L H L H l h l h X X l h X X X OEB0 H H H H H H H H H Disable Disable Disable Disable Disable Disable Disable Disable Disable Disable X X X X OEB1 L L L L L L L L L OEA L L L L L L X L L H H H H H H H H H H H H H H X X L LCAB X X L L H X X X X X X X X X X X X X X X X X LCBA X X X X X X X X X X X L L L L H H X X X SEL0 H H L L L L L X X H H L L H H L L H H L H L L X X X SEL1 L L L L L L L H H L L L L H H L L H H L H H H X X X OUTPUTS An input input input input input input X input input H L H L H L H L H L latched data latched data H L X X Z Bn H** L H** L H** L latched data H** L input input input input input input input input input input X X input input H** H** X
Bn to An register Disable Bn outputs Disable An outputs
Disable Disable L X X X H X
FUNCTION SELECT TABLE
MODE SELECTED Thru mode Register mode (An to Bn) Latch mode (An to Bn) Register mode (Bn to An) Latch mode (Bn to An) NOTES: H = High voltage level L = Low voltage level l = Low voltage level one set-up time prior to the Low-to-High LCXX transition h = High voltage level one set-up time prior to the Low-to-High LCXX transition X = Don't care SEL0 H X L L L H Z -- H** Bn* = = = = = SEL1 L H L H L H
High-impedance (OFF) state Input not externally driven Low-to-High transition Goes to level of pull-up voltage Precaution should be taken to ensure B inputs do not float. If they do, they are equal to Low state. Disable = OEB0 is Low or OEB1 is High.
2000 Apr 18
5
Philips Semiconductors
Product specification
9-bit BTL 3.3V latched/registered/pass-thru Futurebus+ transceiver with 30 termination
FBL22031
LOGIC DIAGRAM
OEB0 OEB1 OEA 46 45 47 D E D A8 14 Clk Q MUX A B 24 B8 Q
MUX A B
Q Q
D D E
D E D A7 12 10 Clk
Q
Q
D Clk
Q
MUX A B
26 28 30
B7
MUX 8 6 D 4 2 E D Clk A1 52 Q MUX A B Q A B
Q
D E 32 34 36 38 B1
BTL
TTL
Q
D Clk
MUX A B
Q
D E
D E D Clk A0 50
Q
Q
D Clk
Q MUX A B
40
B0
MUX A B
Q
D E
Q LCAB SEL0 SEL1 LCBA 18 20 15 16 Decode In Out
D Clk
TMS TCK TDI TDO
42 44 22 21
(JTAG Boundary Scan pins)
LOGIC GND BUS GND BIAS V VCC BG VCC BG GND
= = = = = =
1, 3, 5, 7, 9, 11, 13, 51 25, 27, 29, 31, 33, 35, 37, 39, 41 48 23, 43, 49 17 19 SG00061
2000 Apr 18
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Philips Semiconductors
Product specification
9-bit BTL 3.3V latched/registered/pass-thru Futurebus+ transceiver with 30 termination
FBL22031
ABSOLUTE MAXIMUM RATINGS
Operation beyond the limits set forth in this table may impair the useful life of the device. Unless otherwise noted these limits are over the operating free-air temperature range. SYMBOL VCC VIN IIN VOUT IO OUT TSTG Supply voltage Input voltage Input current Voltage applied to output in High output state Current applied to output in Low output state/High output state Storage temperature AO0 - AO8 B0 - B8 AI0 - AI6, OEB0, OEBn, OEAn B0 - B8 VIN t 0 PARAMETER RATING -0.5 to +4.6 -0.5 to +7.0 -0.5 to +3.5 -50 -0.5 to +7.0 24, -24 200 -65 to +150 UNIT V V V V V mA mA C
RECOMMENDED OPERATING CONDITIONS
SYMBOL PARAMETER COMMERCIAL LIMITS VCC = 3.3V10%; Tamb = -40 to +85C MIN VCC VIH VIL IIK IOH IO OL COB Tamb Supply voltage High-level High level input voltage Low-level Low level input voltage Input clamp current High-level output current Low-level Low level output current Output capacitance on B port Operating free-air temperature range 0 AO0 - AO8 AO0 - AO8 B0 - B8 6 Except B0-B8 B0 - B8 Except B0-B8 B0 - B8 3.0 2.0 1.62 1.55 0.8 1.47 -18 -12 +12 100 7 +70 TYP 3.3 MAX 3.6 V V V V V mA mA mA mA pF C UNIT
LIVE INSERTION SPECIFICATIONS
SYMBOL VBIASV IBIASV S VBn ILM IHM IBnPEAK IO OFF OL tGR Bias pin voltage Bias pin ( BIASV) input DC (I current Bus voltage during prebias Fall current during prebias Rise current during prebias Peak bus current during insertion Power up current Input glitch rejection PARAMETER Voltage difference between the Bias voltage and VCC after the PCB is plugged in. VCC = 0 V, Bias V = 3.6V VCC = 3.3V, Bias V = 3.6V B0 - B8 = 0V, Bias V = 3.3V B0 - B8 = 2V, Bias V = 1.3 to 2.5V B0 - B8 = 1V, Bias V = 3 to 3.6V VCC = 0 to 3.3V, B0 - B8 = 0 to 2.0V, Bias V = 2.7 to 3.6V, OEB0 = 0.8V, tr = 2ns VCC = 0 to 3.3V, OEB0 = 0.8V VCC = 0 to 1.2V, OEB0 = 0 to 5V VCC = 3.3V 1.0 1.35 -1 10 100 100 1.62 LIMITS MIN - TYP - MAX 0.5 1.2 10 2.1 1 UNIT V mA A V A A mA A ns
2000 Apr 18
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Philips Semiconductors
Product specification
9-bit BTL 3.3V latched/registered/pass-thru Futurebus+ transceiver with 30 termination
FBL22031
DC ELECTRICAL CHARACTERISTICS
Over recommended operating free-air temperature range unless otherwise noted. SYMBOL IOH IO OFF PARAMETER High level output current Power-off Power off output current B0 - B8 B0 - B8 TEST CONDITIONS1 VCC = MAX, VIL = MAX, VOH = 1.9V VCC = 0V, VIL = MAX, VOH = 1.9V VCC = 0V, VIL = MAX, VOH = 1.9V @ 85C VCC = MIN to MAX, IOH = -100A VOH High-level output Hi h l ltt voltage AO0 - AO83 VCC = MIN; IOH = -4mA VCC = MIN; IOH = -12mA AO0 - AO83 VO OL Low-level Low level output voltage B0 - B8 VIK Input clamp voltage Control pins II Input leakage current Control/AI0 - AI8 AI0 - AI8 Note 4 IIH IIL IOZH IOZL High-level input current B0 - B8 VCC = MIN; IOL = 4mA VCC = MIN; IOL = 12mA VCC = MIN, IOL = 4mA VCC = MIN, IOL = 100mA VCC = MIN, II = IIK = -18mA VCC = 3.6V; VI = VCC or 100mV VCC = 0V or 3.6V; VI = 5.5V VCC = 3.6V; VI = VCC VCC = 3.6V; VI = 100mV VCC = MAX, VI = 1.9V VCC = MAX, VI = 3.5V, note 5 VCC = MAX, VI = 3.75V, note 5 @ -40C Low level input current Low-level Off-state output current Off-state output current B0 - B8 AO0 - AO8 AO0 - AO8 ICCH B to A ICCL B to A ICC Supply current (total) ICCH A to B ICCL A to B ICCZ VCC = MAX, VI = 0.75V MAX 0 75V VCC = MAX, VO =3V VCC = MAX, VO = 0.5V VCC = MAX, outputs High VCC = MAX, outputs Low VCC = MAX, outputs High VCC = MAX, outputs Low VCC = MAX 18 22 11 11 18 100 100 100 -100 5 -5 32 37 16 16 32 0.5 0.75 1.0 -0.85 1.20 -1.2 1.0 10 1 -5 100 VCC-0.2 2.4 2.0 0.4 0.8 LIMITS MIN TYP2 MAX 100 100 300 UNIT A A A V V V V V V V V A A A A A mA mA A A A mA mA mA mA mA
NOTES: 1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operation conditions for the applicable type. 2. All typical values are at VCC = 3.3V, TA = 25C. 3. Due to test equipment limitations, actual test conditions are VIH = 1.8V and VIL = 1.3V for the B side. 4. Unused pins are at VCC or GND. 5. For B port input voltage between 3 and 5 volt; IIH will be greater than 100mA but the part will continue to function normally (clamping circuit is active).
2000 Apr 18
8
Philips Semiconductors
Product specification
9-bit BTL 3.3V latched/registered/pass-thru Futurebus+ transceiver with 30 termination
FBL22031
AC ELECTRICAL CHARACTERISTICS
B TO A SPECIFICATIONS SYMBOL PARAMETER TEST CONDITION Waveform 4 Waveform 1, 2 Waveform 1, 2 Waveform 1, 2 Waveform 1, 2 Waveform 1, 2 Waveform 1, 2 Waveform 5, 6 Waveform 5, 6 Test Circuit and Waveforms Waveform 3 Waveform 2 0.5 0.5 1.0 1.0 120 2.3 2.6 3.2 3.5 6.8 5.5 2.1 2.3 2.7 2.5 2.4 2.6 2.6 3.4 2.1 1.2 Tamb = +25C, VCC = 3.3V, MIN fMAX tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPZH tPHZ tPZL tPLZ tTLH tTHL tSK(o) tSK(p) Maximum clock frequency Propagation delay (thru mode) Bn to An Propagation delay (transparent latch) Bn to An Propagation delay LCBA to An (latch) Propagation delay LCBA to An (register) Propagation delay SEL0 or SEL1 to An (inverting) Propagation delay SEL0 or SEL1 to An (non-inverting) Output enable time from High or Low OEA to An Output disable time to High or Low OEA to An Output transition time, An Port 10% to 90%, 90% to 10% Output to output skew for multiple channels1 Pulse skew2 tPHL - tPLH MAX TYP 150 5.4 5.6 6.5 6.3 10.4 9.8 4.9 5.2 6.5 6.3 6.6 6.2 5.8 5.4 5.4 3.1 8.9 9.1 10.1 9.3 14.4 14.7 8.4 8.3 10.7 10.5 11.3 10.2 9.3 7.5 9.1 5.4 1.7 2.1 2.4 2.9 5.1 4.3 1.2 1.8 1.8 2.0 1.8 2.1 1.9 2.9 1.6 1.0 0.7 0.5 10.1 10.3 11.6 10.3 16.9 16.8 9.7 9.4 12.8 11.8 13.0 11.6 10.7 9.0 10.1 6.0 3.0 2.0 1.5 1.5 MAX Tamb = -40 to +85C, VCC = 3.3V10%, MIN MAX MHz ns ns ns ns ns ns ns ns ns ns ns UNIT
NOTES: 1. tPNactual - tPMactual for any data input to output path compared to any other data input to output path where N and M are either LH or HL. Skew times are valid only under same test conditions (temperature, VCC, loading, etc.). tSK (0) compares tPLH on a given path to tPLH on any other path or compares tPHL on a given path to tPHL on any other path. 2. tSK(p) is used to quantify duty cycle characteristics. In essence it compares the input signal duty cycle to the corresponding output signal duty cycle (50MHz input frequency and 50% duty cycle, tested on data paths only).
2000 Apr 18
9
Philips Semiconductors
Product specification
9-bit BTL 3.3V latched/registered/pass-thru Futurebus+ transceiver with 30 termination
FBL22031
AC ELECTRICAL CHARACTERISTICS
A TO B SYMBOL PARAMETER TEST CONDITION 1.2 1.2 1.2 1.3 7.2 7.2 1.2 1.4 1.2 1.6 1.9 1.9 1.2 1.2 9 LOAD SPECIFICATIONS Tamb = -40 to +85C, VCC = 3.3V10%, MAX 8.1 6.5 8.6 7.7 17.4 15.5 8.8 7.5 9.8 8.1 9.9 7.9 8.4 6.7 MIN 1.0 1.0 1.0 1.0 5.3 5.6 1.0 1.0 1.0 1.1 1.0 1.3 1.0 1.0 1.2 0.4 0.4 0.3 1.0 1.0 MAX 9.1 6.9 9.5 8.4 20.5 17.8 10.2 8.4 11.4 9.9 11.2 9.0 9.8 8.0 3.0 1.5 2.0 1.5 ns ns ns ns ns ns ns ns ns ns UNIT Tamb = +25C, VCC = 3.3V, MIN tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tTLH tTHL tSK(o) tSK(p) Propagation delay (thru latch) An to Bn Propagation delay (transparent latch) An to Bn Propagation delay LCAB to Bn (latch) Propagation delay LCAB to Bn (register) Propagation delay SEL0 or SEL1 to Bn (inverting) Propagation delay SEL0 or SEL1 to Bn (non-inverting) OEBn to Bn Output transition time, Bn Port (1.3V to 1.8V) Output to output skew for multiple channels1 Pulse skew2 tPHL - tPLH MAX Waveform 1, 2 Waveform 1, 2 Waveform 1, 2 Waveform 1, 2 Waveform 1, 2 Waveform 1, 2 Waveform 1, 2 Test Circuit and Waveforms Waveform 3 Waveform 2 TYP 3.5 3.1 3.8 4.0 12.0 11.1 4.4 4.3 5.1 4.6 5.6 4.7 4.0 3.7
NOTES: 1. tPNactual - tPMactual for any data input to output path compared to any other data input to output path where N and M are either LH or HL. Skew times are valid only under same test conditions (temperature, VCC, loading, etc.). tSK (0) compares tPLH on a given path to tPLH on any other path or compares tPHL on a given path to tPHL on any other path. 2. tSK(p) is used to quantify duty cycle characteristics. In essence it compares the input signal duty cycle to the corresponding output signal duty cycle (50MHz input frequency and 50% duty cycle, tested on data paths only).
2000 Apr 18
10
Philips Semiconductors
Product specification
9-bit BTL 3.3V latched/registered/pass-thru Futurebus+ transceiver with 30 termination
FBL22031
AC ELECTRICAL CHARACTERISTICS
A TO B SYMBOL PARAMETER TEST CONDITION 1.2 1.3 1.2 1.6 6.6 6.7 1.2 1.2 1.3 1.7 1.8 1.8 1.3 1.7 16.5 LOAD SPECIFICATIONS Tamb = -40 to +85C, VCC = 3.3V10%, MAX 7.4 5.9 8.0 7.3 17.6 15.7 8.8 7.6 9.7 8.6 9.8 7.9 8.1 6.7 MIN 1.0 1.1 1.0 1.2 4.8 5.2 1.0 1.0 1.0 1.3 1.0 1.1 1.0 1.0 1.2 0.4 0.4 0.3 1.0 1.0 MAX 8.7 6.4 9.3 8.1 20.6 18.1 10.1 8.5 11.2 9.6 11.3 9.0 9.4 7.8 3.0 1.5 2.0 1.5 ns ns ns ns ns ns ns ns ns ns UNIT Tamb = +25C, VCC = 3.3V, MIN tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tTLH tTHL tSK(o) tSK(p) Propagation delay (thru latch) An to Bn Propagation delay (transparent latch) An to Bn Propagation delay LCAB to Bn (latch) Propagation delay LCAB to Bn (register) Propagation delay SEL0 or SEL1 to Bn (inverting) Propagation delay SEL0 or SEL1 to Bn (non-inverting) OEBn to Bn Output transition time, Bn Port (1.3V to 1.8V) Output to output skew for multiple channels1 Pulse skew2 tPHL - tPLH MAX Waveform 1, 2 Waveform 1, 2 Waveform 1, 2 Waveform 1, 2 Waveform 1, 2 Waveform 1, 2 Waveform 1, 2 Test Circuit and Waveforms Waveform 3 Waveform 2 TYP 4.1 3.5 4.3 4.3 11.8 10.9 4.3 4.1 5.3 4.9 5.6 4.7 4.4 4.0
NOTES: 1. tPNactual - tPMactual for any data input to output path compared to any other data input to output path where N and M are either LH or HL. Skew times are valid only under same test conditions (temperature, VCC, loading, etc.). tSK (0) compares tPLH on a given path to tPLH on any other path or compares tPHL on a given path to tPHL on any other path. 2. tSK(p) is used to quantify duty cycle characteristics. In essence it compares the input signal duty cycle to the corresponding output signal duty cycle (50MHz input frequency and 50% duty cycle, tested on data paths only).
2000 Apr 18
11
Philips Semiconductors
Product specification
9-bit BTL 3.3V latched/registered/pass-thru Futurebus+ transceiver with 30 termination
FBL22031
AC SETUP REQUIREMENTS (Commercial)
LIMITS TEST CONDITION Tamb = +25C, VCC = 3.3V, Tamb = -40 to +85C, VCC = 3.3V10%,
SYMBOL
PARAMETER
CL = 50pF (A side) / CD = 30pF (B side) RL = 500 (A side) / RU = 16.5 (B side) MIN TYP MIN 1.5 1.5 1.0 1.0 6.0 4.5 0.0 0.0 3.0 3.0 1.3 1.3 1.0 1.0 5.0 4.0 0.0 0.0 3.0 3.0
UNIT
ts(H) ts(L) th(H) th(L) ts(H) ts(L) th(H) th(L) tw(H) tw(L)
Setup time An to LCAB Hold time An to LCAB Setup time Bn to LCBA Hold time Bn to LCBA Pulse width, High or Low LCAB or LCBA
Waveform 4 Waveform 4 Waveform 4 Waveform 4 Waveform 4
ns ns ns ns ns
AC WAVEFORMS
Input VM tPLH Output VM VM tPHL VM Output Input VM tw (input) tPHL VM VM tPLH tw (output) VM
Waveform 1. Propagation Delay for Data or Output Enable to Output
Waveform 2. Propagation Delay for Data or Output Enable to Output
An, Bn
VM tSK(o)
An, Bn
An, Bn
VM
LCAB, LCBA
Waveform 3. Output to Output Skew
VM tPZH An VM VM tPHZ VOH -0.3V OV
Waveform 4. Setup and Hold Times, Pulse Widths and Maximum Frequency
OEA VM tPZL An VM VM tPLZ VOL +0.3V
OEA
Waveform 5. 3-State Output Enable Time to High Level and Output Disable Time from High Level
Waveform 6. 3-State Output Enable Time to Low Level and Output Disable Time from Low Level
SG00062
NOTE: VM = 1.55V for Bn, VM = 1.5V for all others. The shaded areas indicate when the input is permitted to change for predictable output performance.
2000 Apr 18
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II IIIIII II IIIIII
VM
ts
th
VM
ts tw(L)
th
tw(H)
VM
1/fMAX
Philips Semiconductors
Product specification
9-bit BTL 3.3V latched/registered/pass-thru Futurebus+ transceiver with 30 termination
FBL22031
TEST CIRCUIT AND WAVEFORMS
VCC 7.0V RL NEGATIVE PULSE 90% VM 10% tTHL CL RL tW VM 10% LOW V tTLH 90% AMP (V)
VIN PULSE GENERATOR RT D.U.T.
VOUT
(tf) (tr)
90% VM tW
(tr) (tf)
AMP (V)
tTLH 90% POSITIVE PULSE VM 10%
tTHL
Test Circuit for 3-State Outputs on A Port SWITCH POSITION TEST tPLZ, tPZL All other SWITCH closed open
VCC BIAS V VIN PULSE GENERATOR RT D.U.T. 2.0V (for RU = 9 ) 2.1V (for RU = 16.5 )
10%
LOW V
VM = 1.55V for Bn, VM = 1.5V for all others.
Input Pulse Definitions Family FB+ A Port B Port INPUT PULSE REQUIREMENTS Amplitude 3.0V 2.0V Low V 0.0V 1.0V Rep. Rate 1MHz 1MHz tW tTLH tTHL 2.5ns 2.0ns
500ns 2.5ns 500ns 2.0ns
VOUT
RU
CD
Test Circuit for Outputs on B Port
DEFINITIONS: RL = Load Resistor; see AC CHARACTERISTICS for value. CL = Load capacitance includes jig and probe capacitance; see AC CHARACTERISTICS for value. RT = Termination resistance should be equal to ZOUT of pulse generators. CD = Load capacitance includes jig and probe capacitance; see AC CHARACTERISTICS for value. RU = Pull up resistor; see AC CHARACTERISTICS for value.
SG00063
2000 Apr 18
13
Philips Semiconductors
Product specification
9-bit BTL 3.3V latched/registered/pass-thru Futurebus+ transceiver with 30 termination
FBL22031
QFP52: plastic quad flat package; 52 leads (lead length 1.6 mm); body 10 x 10 x 2.0 mm
SOT379-1
2000 Apr 18
14
Philips Semiconductors
Product specification
9-bit BTL 3.3V latched/registered/pass-thru Futurebus+ transceiver with 30 termination
FBL22031
NOTES
2000 Apr 18
15
Philips Semiconductors
Product specification
9-bit BTL 3.3V latched/registered/pass-thru Futurebus+ transceiver with 30 termination
FBL22031
Data sheet status
Data sheet status Objective specification Preliminary specification Product specification Product status Development Qualification Definition [1] This data sheet contains the design target or goal specifications for product development. Specification may change in any manner without notice. This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. This data sheet contains final specifications. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product.
Production
[1] Please consult the most recently issued datasheet before initiating or completing a design.
Definitions
Short-form specification -- The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition -- Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information -- Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification.
Disclaimers
Life support -- These products are not designed for use in life support appliances, devices or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes -- Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088-3409 Telephone 800-234-7381 (c) Copyright Philips Electronics North America Corporation 2000 All rights reserved. Printed in U.S.A. Date of release: 04-00 Document order number: 9397 750 07091
Philips Semiconductors
2000 Apr 18 16

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